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LTC2308 1 2308f frequency (khz) 0 C140 magnitude (db) C120 C100 C80 0 C40 100 150 250 C20 C60 C130 C110 C90 C10 C50 C30 C70 50 200 2308 g03 f smpl = 500khz sinad = 73.6db thd = C89.5db typical application features applications description low noise, 500ksps, 8-channel, 12-bit adc the ltc ? 2308 is a low noise, 500ksps, 8-channel, 12-bit adc with an spi/microwire compatible serial interface. this adc includes an internal reference and a fully differ- ential sample-and-hold circuit to reduce common-mode noise. the internal conversion clock allows the external serial output data clock (sck) to operate at any frequency up to 40mhz. the LTC2308 operates from a single 5v supply and draws just 3.5ma at a sample rate of 500ksps. the auto-shutdown feature reduces the supply current to 200a at a sample rate of 1ksps. the LTC2308 is packaged in a small 24-pin 4mm 4mm qfn. the internal 2.5v reference and 8-channel multiplexer further reduce pcb board space requirements. the low power consumption and small size make the LTC2308 ideal for battery operated and portable appli- cations, while the 4-wire spi compatible serial interface makes this adc a good match for isolated or remote data acquisition systems. 8192 point fft, f in = 1khz 12-bit resolution 500ksps sampling rate low noise: sinad = 73.3db guaranteed no missing codes single 5v supply auto-shutdown scales supply current with sample rate low power: 17.5mw at 500ksps 0.9mw nap mode 35w sleep mode internal reference internal 8-channel multiplexer internal conversion clock spi/microwire tm compatible serial interface unipolar or bipolar input ranges (software selectable) separate output supply ov dd (2.7v to 5.25v) 24-pin 4mm 4mm qfn package high speed data acquisition industrial process control motor control accelerometer measurements battery operated instruments isolated and/or remote data acquisition , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com sdi sdo sck convst 2308 ta01 serial port analog input mux ch0-ch7 analog inputs 0v to 4.096v unipolar p 2.048v bipolar refcomp serial data link to asic, pld, mpu, dsp or shift register internal 2.5v ref LTC2308 av dd dv dd ov dd gnd 0.1 f 2.7v to 5.25 v 5v 12-bit 500ksps adc + C 2.2 f 0.1 f 0.1 f 10 f 10 f 10 f 0.1 f v ref
LTC2308 2 2308f pin configuration absolute maximum ratings supply voltage (av dd , dv dd , ov dd ) ...........................6v analog input voltage (note 3) ch0 - ch7, com, ref, refcomp ....................(gnd ?0.3v) to (av dd + 0.3v) digital input voltage (note 3) ...................... (gnd ?0.3v) to (dv dd + 0.3v) digital output voltage ..... (gnd ?0.3v) to (ov dd + 0.3v) power dissipation ...............................................500mw operating temperature range LTC2308c ................................................ 0c to 70c LTC2308i ............................................. ?40c to 85c storage temperature range ................... ?65c to 150c (notes 1, 2) 24 25 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ch3 ch4 ch5 ch6 ch7 com gnd sd0 sck sdi convst av dd ch2 ch1 ch0 dv dd gnd ov dd v ref refcomp gnd gnd gnd av dd t jmax = 150c, ja = 37c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information converter and multiplexer characteristics parameter conditions min typ max units resolution (no missing codes) o 12 bits integral linearity error (note 6) o 0.3 1 lsb differential linearity error o 0.25 1 lsb bipolar zero error (note 7) o 1 6 lsb bipolar zero error drift 0.002 lsb/c bipolar zero error match o 0.3 3 lsb unipolar zero error (note 7) o 0.5 3 lsb unipolar zero error drift 0.002 lsb/c unipolar zero error match o 0.3 2 lsb the o denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4, 5) lead free finish tape and reel part marking* package description temperature range LTC2308cuf#pbf LTC2308iuf#pbf LTC2308cuf#trpbf LTC2308iuf#trpbf 2308 2308 24-lead (4mm 4mm) plastic qfn 24-lead (4mm 4mm) plastic qfn 0c to 70c ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
LTC2308 3 2308f parameter conditions min typ max units bipolar full-scale error external reference (note 8) 1 9 lsb bipolar full-scale error drift external reference 0.05 lsb/c bipolar full-scale error match 0.5 3 lsb unipolar full-scale error external reference (note 8) 1.5 8 lsb unipolar full-scale error drift external reference 0.05 lsb/c unipolar full-scale error match 0.4 3 lsb converter and multiplexer characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 4, 5) analog input the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in + absolute input range (ch0 to ch7) (note 9) C0.05 av dd v v in C absolute input range (ch0 to ch7, com) unipolar (note 9) bipolar (note 9) C0.05 C0.05 av dd /2 av dd v v v in + C v in C input differential voltage range v in = v in + C v in C (unipolar) v in = v in + C v in C (bipolar) 0 to refcomp refcomp/2 v v i in analog input leakage current 1 a c in analog input capacitance sample mode hold mode 55 5 pf pf cmrr input common mode rejection ratio 70 db dynamic accuracy the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c and a in = C1dbfs. (notes 4, 10) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 1khz 71 73.3 db snr signal-to-noise ratio f in = 1khz 71 73.4 db thd total harmonic distortion f in = 1khz, first 5 harmonics C90 C78 db sfdr spurious free dynamic range f in = 1khz C90 C80 db channel-to-channel isolation f in = 1khz C109 db full linear bandwidth (note 11) 700 khz C3db input linear bandwidth 25 mhz aperture delay 13 ns transient reponse full-scale step 240 ns
LTC2308 4 2308f internal reference characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) parameter conditions min typ max units v ref output voltage i out = 0 2.47 2.50 2.53 v v ref output tempco i out = 0 25 ppm/c v ref output impedance C0.1ma i out 0.1ma 8 k v refcomp output voltage i out = 0 4.096 v v ref line regulation av dd = 4.75v to 5.25v 0.8 mv/v digital inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ih high level input voltage dv dd = 5.25v 2.4 v v il low level input voltage dv dd = 4.75v 0.8 v i in high level input current v in = v dd 10 a c in digital input capacitance 5pf v oh high level output voltage ov dd = 4.75v, i out = C10a ov dd = 4.75v, i out = C200a 4 4.74 v v v ol low level input voltage ov dd = 4.75v, i out = 160a ov dd = 4.75v, i out = 1.6ma 0.05 0.4 v v i oz hi-z output leakage v out = 0v to ov dd , convst high 10 a c oz hi-z output capacitance convst high 15 pf i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma power requirements the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units av dd analog supply voltage 4.75 5 5.25 v dv dd digital supply voltage 4.75 5 5.25 v ov dd output driver supply voltage 2.7 5.25 v i dd supply current nap mode sleep mode c l = 25pf convst = 5v, conversion done convst = 5v, conversion done 3.5 180 7 4.2 400 20 ma a a p d power dissipation nap mode sleep mode 17.5 0.9 35 mw mw w
LTC2308 5 2308f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with av dd , dv dd and ov dd wired together (unless otherwise noted). note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. these products can handle input currents greater than 100ma below ground or above v dd without latchup. note 4: av dd = 5v, dv dd = 5v, ov dd = 5v, f smpl = 500khz, internal reference unless otherwise speci? ed. note 5: linearity, offset and full-scale speci? cations apply for a single- ended analog input with respect to com. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. timing characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl(max) maximum sampling frequency 500 khz f sck shift clock frequency 40 mhz t whconv convst high time (note 9) 20 ns t hd hold time sdi after sck 2.5 ns t sudi setup time sdi valid before sck 0ns t whclk sck high time f sck = f sck(max) 10 ns t wlclk sck low time f sck = f sck(max) 10 ns t wlconvst convst low time during data transfer (note 9) 410 ns t hconvst hold time convst low after last sck (note 9) 20 ns t conv conversion time 1.3 1.6 s t acq acquisition time 7th sck to convst (note 9) 240 ns t refwake refcomp wakeup time (note 12) c refcomp = 10f, c ref = 2.2f 200 ms t ddo sdo data valid after sck c l = 25pf (note 9) 10.8 12.5 ns t hdo sdo hold time after sck c l = 25pf 4ns t en sdo valid after convst c l = 25pf 11 15 ns t dis bus relinquish time c l = 25pf 11 15 ns t r sdo rise time c l = 25pf 4 ns t f sdo fall time c l = 25pf 4 ns t cyc total cycle time 2s note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code ? ickers between 0000 0000 0000 and 1111 1111 1111. unipolar zero error is the offset voltage measured from +0.5lsb when the output code ? ickers between 0000 0000 0000 and 0000 0000 0001. note 8: full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal ? rst and last code transitions and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. note 9: guaranteed by design, not subject to test. note 10: all speci? cations in db are referred to a full-scale 2.048v input with a 2.5v reference voltage. note 11 : full linear bandwidth is de? ned as the full-scale input frequency at which the sinad degrades to 60db or 10 bits of accuracy. note 12: refcomp wakeup time is the time required for the refcomp pin to settle within 0.5lsb at 12-bit resolution of its ? nal value after waking up from sleep mode.
LTC2308 6 2308f frequency (khz) C120 crosstalk (db) C100 C90 C70 C60 0.1 10 100 1000 3208 g04 C140 1 C80 C110 C130 frequency (khz) 1 50 snr (db) 70 75 80 10 100 1000 3208 g05 65 60 55 frequency (khz) 1 50 sinad (db) 70 75 80 10 100 1000 3208 g06 65 60 55 frequency (khz) 1 C80 thd (db) C70 C60 10 100 1000 3208 g07 C90 C85 C75 C65 C95 C100 sampling frequency (ksps) 1 2.0 supply current (ma) 2.5 3.0 3.5 10 100 1000 3208 g08 1.5 1.0 0.5 0 output code 0 dnl (lsb) 0 0.25 0.50 4096 2308 g02 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 frequency (khz) 0 C140 magnitude (db) C120 C100 C80 0 C40 100 150 250 C20 C60 C130 C110 C90 C10 C50 C30 C70 50 200 2308 g03 snr = 73.7db sinad = 73.6db thd = C89.5db output code 0 inl (lsb) 0 0.25 0.50 4096 2308 g01 C0.25 C0.50 C1.00 1024 2048 3072 C0.75 1.00 0.75 typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code 1khz sine wave 8192 point fft plot crosstalk vs frequency for an adjacent pair snr vs input frequency sinad vs input frequency thd vs input frequency supply current vs sampling frequency supply current vs temperature temperature ( o c) C50 C25 0 supply current (ma) 2 5 0 50 75 3208 g09 1 4 3 25 100 125 t a = 25c, av dd = dv dd = ov dd = 5v, f smpl = 500ksps, internal reference, unless otherwise noted.
LTC2308 7 2308f temperature ( o c) C50 C25 0 sleep current (a) 4 10 0 50 75 3208 g10 2 8 6 25 100 125 temperature ( o c) C50 C25 0 leakage current (na) 400 1000 0 50 75 3208 g11 200 800 600 25 100 125 ch (on) ch (off) f smpl = 0ksps temperature (c) C50 0 offset (lsb) 0.5 1.0 1.5 C25 0 25 50 2308 g12 75 100 125 external reference bipolar unipolar temperature ( o c) C50 C25 C6 full-scale error (lsb) C2 4 0 50 75 2308 g13 C4 2 0 25 100 125 external reference bipolar unipolar typical performance characteristics sleep current vs temperature analog input leakage current vs temperature offset vs temperature full-scale error vs temperature t a = 25c, av dd = dv dd = ov dd = 5v, f smpl = 500ksps, internal reference, unless otherwise noted.
LTC2308 8 2308f pin functions ch3-ch7 (pins 1, 2, 3, 4, 5): channel 3 to channel 7 analog inputs. ch3 C ch7 can be con? gured as single- ended or differential input channels. see the analog input multiplexer section. com (pin 6): common input. this is the reference point for all single-ended inputs. it must be free of noise and connected to ground for unipolar conversions and midway between gnd and refcomp for bipolar conversions. v ref (pin 7): 2.5v reference output. bypass to gnd with a minimum 2.2f tantalum capacitor or low esr ceramic capacitor. the internal reference may be over driven by an external 2.5v reference at this pin. refcomp (pin 8): reference buffer output. bypass to gnd with a 10f tantalum and 0.1f ceramic capacitor in parallel. nominal output voltage is 4.096v. gnd (pins 9, 10, 11, 18, 20): ground. all gnd pins must be connected to a solid ground plane. av dd (pins 12, 13): 5v analog supply. the range of av dd is 4.75v to 5.25v. bypass av dd to gnd with a 0.1f ceramic and a 10f tantalum capacitor in parallel. convst (pin 14): conversion start. a rising edge at convst begins a conversion. for best performance, ensure that convst returns low within 40ns after the conversion starts or after the conversion ends. sdi (pin 15): serial data input. the sdi serial bit stream con? gures the adc and is latched on the rising edge of the ? rst 6 sck pulses. sck (pin 16): serial data clock. sck synchronizes the serial data transfer. the serial data input at sdi is latched on the rising edge of sck. the serial data output at sdo transitions on the falling edge of sck. sdo (pin 17): serial data out. sdo outputs the data from the previous conversion. sdo is shifted out serially on the falling edge of each sck pulse. ov dd (pin 19): output driver supply. bypass ov dd to gnd with a 0.1f ceramic capacitor close to the pin. the range of ov dd is 2.7v to 5.25v. dv dd (pin 21): 5v digital supply. the range of dv dd is 4.75v to 5.25v. bypass dv dd to gnd with a 0.1 f ceramic and a 10f tantalum capacitor in parallel. ch0-ch2 (pins 22, 23, 24): channel 0 to channel 2 analog inputs. ch0 C ch2 can be con? gured as single- ended or differential input channels. see the analog input multiplexer section. gnd (pin 25): exposed pad ground. must be soldered directly to ground plane.
LTC2308 9 2308f block diagram ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com sdi sdo sck convst 2308 bd serial port analog input mux refcomp internal 2.5v ref av dd dv dd ov dd gnd 12-bit 500ksps adc LTC2308 8k gain = 1.6384x + C v ref test circuit sdo 3k c l v dd test point 2308 tc01 load circuit for t dis waveform 2, t en load circuit for t dis waveform 1 sdo 3k test point 2308 tc02 c l
LTC2308 10 2308f timing diagram sck sdo v il t ddo t hdo v oh v ol 2308 td01 2308 td04 convst sdo t en sdo t r t f 2308 td05 v oh v ol sdo waveform 1 (see note 1) v ih t dis 90% 10% sdo waveform 2 (see note 2) convst note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 2308 td02 2308 td03 sck sdi t wlclk t whclk t hd t sudi voltage waveforms for sdo delay times, t ddo and t hdo voltage waveforms for t dis voltage waveforms for sdo rise and fall times t r , t f voltage waveforms for t en t wlclk (sck low time) t whclk (sck high time) t hd (hold time sdi after sck ) t sudi (setup time sdi stable before sck )
LTC2308 11 2308f applications information overview the LTC2308 is a low noise, 500ksps, 8-channel, 12-bit successive approximation register (sar) a/d converter. the LTC2308 includes a precision internal reference, a con? gurable 8-channel analog input multiplexer (mux) and an spi-compatible serial port for easy data transfers. the adc may be con? gured to accept single-ended or differential signals and can operate in either unipolar or bipolar mode. a sleep mode option is also provided to save power during inactive periods. conversions are initiated by a rising edge on the convst input. once a conversion cycle has begun, it cannot be restarted. between conversions, a 6-bit input word (d in ) at the sdi input con? gures the mux and programs vari- ous modes of operation. as the d in bits are shifted in, data from the previous conversion is shifted out on sdo. after the 6 bits of the d in word have been shifted in, the adc begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out. the acquire phase requires a minimum time of 240ns for the sample-and-hold capacitors to acquire the analog input signal. during the conversion, the internal 12-bit capacitive charge-redistribution dac output is sequenced through a successive approximation algorithm by the sar starting from the most signi? cant bit (msb) to the least signi? cant bit (lsb). the sampled input is successively compared with binary weighted charges supplied by the capacitive dac using a differential comparator. at the end of a conver- sion, the dac output balances the analog input. the sar contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out. programming the LTC2308 the various modes of operation of the LTC2308 are programmed by a 6-bit d in word. the sdi data bits are loaded on the rising edge of sck, with the s/d bit loaded on the ? rst rising edge and the slp bit on the sixth rising edge (see figure 8 in the timing and control section). the input data word is de? ned as follows: s/d o/s s1 s0 uni slp s/d = single-ended/ differential bit o/s = odd/ sign bit s1 = address select bit 1 s0 = address select bit 0 uni = unipolar/ bipolar bit slp = sleep mode bit
LTC2308 12 2308f table 1. channel con? guration s/do/ss1s001234567com 0000+C 0001 +C 0010 +C 0011 +C 0100C+ 0101 C+ 0110 C+ 0111 C+ 1000+ C 1001 + C 1010 + C 1011 + C 1100 + C 1101 + C 1110 + C 1111 + C figure 2. driving com in unipolar and bipolar modes com refcomp/2 com unipolar mode bipolar mode 2308 f02 + C figure 1a. example mux con? gurations figure 1b. changing the mux assignment on the fly ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com ( C ) 8 single-ended + + + + + + + 4 differential + ( C ) + + ( C ) + ( C ) + ( C ) C ( + ) C ( + ) C ( + ) C ( + ) com ( C ) combinations of differential and single-ended + + + + + + C C { { { { { { 2308 f01a ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com (unused) com ( C ) 1st conversion 2nd conversion + C + C + C + + { { { { ch2 ch3 ch4 ch5 ch2 ch3 ch4 ch5 2308 f01b analog input multiplexer the analog input mux is programmed by the s/d, o/s, s1 and s0 bits of the d in word. table 1 lists the mux con? gurations for all combinations of the con? guration bits. figure 1a shows several possible mux con? gurations and figure 1b shows how the mux can be recon? gured from one conversion to the next. driving the analog inputs the analog inputs of the LTC2308 are easy to drive. each of the analog inputs can be used as a single-ended input relative to the com pin (ch0-com, ch1-com, etc.) or in differential input pairs (ch0 and ch1, ch2 and ch3, ch4 and ch5, ch6 and ch7). figure 2 shows how to drive com for single-ended inputs in unipolar and bipolar modes. regardless of the mux con? guration, the + and C inputs are sampled at the same instant. any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors during the acquire mode. in conversion mode, the analog inputs draw only a small leakage current. if the source impedance of the applications information
LTC2308 13 2308f driving circuit is low, the adc inputs can be driven directly. otherwise, more acquisition time should be allowed for a source with higher impedance. input filtering the noise and distortion of the input ampli? er and other circuitry must be considered since they will add to the adc noise and distortion. therefore, noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. the analog inputs of the LTC2308 can be modeled as a 55pf capacitor (c in ) in series with a 100 resistor (r on ) as shown in figure 3a. c in gets switched to the selected input once during each conversion. large ? lter rc time constants will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (t acq ) if dc accuracy is important. when using a ? lter with a large c filter value (e.g. 1f), the inputs do not completely settle and the capacitive input switching currents are averaged into a net dc current (i dc ). in this case, the analog input can be modeled by an applications information figure 3b. analog input equivalent circuit for large filter capacitances figure 4b. optional rc input filtering for differential inputs 2308 f04a ch0 com LTC2308 refcomp 2000pf 10f 0.1f 50 analog input 1000pf 2308 f04b ch0 ch1 LTC2308 refcomp 1000pf 1000pf 10f 0.1f 50 50 differential analog inputs equivalent resistance (r eq = 1/(f smpl ? c in )) in series with an ideal voltage source (v refcomp /2) as shown in figure 3b. the magnitude of the dc current is then approximately i dc = (v in - v refcomp /2)/r eq , which is roughly propor- tional to v in . to prevent large dc drops across the resistor r filter , a ? lter with a small resistor and large capacitor should be chosen. when running at the minimum cycle time of 2s, the input current equals 106a at v in = 5v, which amounts to a full-scale error of 0.5lsbs when using a ? lter resistor (r filter ) of 4.7 . applications requiring lower sample rates can tolerate a larger ? lter resistor for the same amount of full-scale error. figures 4a and 4b show respective examples of input ? ltering for single-ended and differential inputs. for the single-ended case in figure 4a, a 50 source resistor and a 2000pf capacitor to ground on the input will limit the input bandwidth to 1.6mhz. high quality capacitors and resistors should be used in the rc ? lter since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. v in input ch0-ch7 r on = 100 c in = 55pf c 1 r source 2308 f03a LTC2308 v in input ch0-ch7 v refcomp /2 r eq = 1/(f smpl ? c in ) c filter r filter i dc 2308 f03b LTC2308 + C figure 4a. optional rc input filtering for single-ended input figure 3a. analog input equivalent circuit
LTC2308 14 2308f dynamic performance fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 5 shows a typical sinad of 73.3db with a 500khz sampling rate and a 1khz input. a snr of 73.4db can be achieved with the LTC2308. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency(f smpl /2). thd is expressed as: thd vvv v v n = ++ + 20 2 2 3 2 4 22 1 log ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. internal reference the LTC2308 has an on-chip, temperature compensated bandgap reference that is factory trimmed to 2.5v (refer to figure 6a). it is internally connected to a reference ampli? er and is available at v ref (pin 7). v ref should be bypassed to gnd with a 2.2f tantalum capacitor for stability and to minimize noise. an 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required as shown in figure 6b. the reference ampli? er gains the v ref voltage by 1.638 to 4.096v at refcomp (pin 8). to compensate the reference ampli? er, bypass refcomp with a 10f ceramic or tantalum capacitor in parallel with a 0.1f ceramic capacitor for best noise performance. internal conversion clock the internal conversion clock is factory trimmed to achieve a typical conversion time (t conv ) of 1.3s and a maximum conversion time of 1.6s over the full operat- ing temperature range. with a typical acquisition time of 240ns, a throughput sampling rate of 500ksps is tested and guaranteed. applications information figure 5. 1khz sine wave 8192 point fft plot frequency (khz) 0 C140 magnitude (db) C120 C100 C80 0 C40 100 150 250 C20 C60 C130 C110 C90 C10 C50 C30 C70 50 200 2308 f05
LTC2308 15 2308f digital interface the LTC2308 communicates via a standard 4-wire spi compatible digital interface. the rising edge of convst initiates a conversion. after the conversion is ? nished, pull convst low to enable the serial output (sdo). the adc shifts out the digital data in 2s complement format when operating in bipolar mode or in straight binary format when in unipolar mode, based on the setting of the uni bit. for best performance, ensure that convst returns low within 40ns after the conversion starts (i.e., before the ? rst bit decision) or after the conversion ends. if convst is low when the conversion ends, the msb bit will appear at sdo at the end of the conversion and the adc will remain powered up. timing and control the start of a conversion is triggered by a rising edge at convst. once initiated, a new conversion cannot be re- started until the current conversion is complete. figures 8 and 9 show the timing diagrams for two different examples of convst pulses. example 1 (figure 8) shows convst staying high after the conversion ends. if convst is high after the t conv period, the LTC2308 enters nap or sleep mode, depending on the setting of slp bit from the d in word that was shifted in after the previous conversion. (see nap mode and sleep mode for more detail). when convst returns low, the adc wakes up and the most signi? cant bit (msb) of the output data sequence at sdo becomes valid after the serial data bus is enabled. all other data bits from sdo transition on the falling edge of each sck pulse. con? guration data (d in ) is loaded into the LTC2308 at sdi, starting with the ? rst sck rising edge after convst returns low. the s/d bit is loaded on the ? rst sck rising edge. example 2 (figure 9) shows convst returning low be- fore the conversion ends. in this mode, the adc and all internal circuitry remain powered up. when the conver- sion is complete, the msb of the output data sequence at sdo becomes valid after the data bus is enabled. at this point(t conv 1.3s after the rising edge of convst), puls- ing sck will shift data out at sdo and load con? guration data (d in ) into the LTC2308 at sdi. the ? rst sck rising edge loads the s/d bit into the LTC2308. sdo transitions on the falling edge of each sck pulse. applications information figure 6a. LTC2308 reference circuit figure 6b. using the lt1790a-2.5 as an external reference r2 r3 reference amp 0.1f 10f 2.2f refcomp gnd v ref r1 8k 2.5v 4.096v LTC2308 2308 f06a bandgap reference 0.1f 10f 2308 f06b lt1790a-2.5 v out v in 5v v ref LTC2308 gnd refcomp + 2.2f 0.1 m f
LTC2308 16 2308f dv dd , bypass 10 f, 0603 v ref , bypass 2.2 f, 1206 av dd , bypass 10 f || 0.1 f, 0603 0v dd , bypass 10 f, 0603 refcomp , bypass 10 f || 0.1 f, 0603 note: second layer of board is a solid ground plane. figures 8 and 9 are the transfer characteristics for the bipolar and unipolar modes. data is output at sdo in 2s complement format for bipolar readings and in straight binary for unipolar readings. nap mode the adc enters nap mode when convst is held high after the conversion is complete (t conv ) if the slp bit is set to a logic 0. the supply current decreases to 180a in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. for example, the LTC2308 draws an average of 200a with a 1ksps sampling rate. the LTC2308 keeps only the reference(v ref ) and reference buffer(refcomp) circuitry active when in nap mode. sleep mode the adc enters sleep mode when convst is held high after the conversion is complete (t conv ) if the slp bit is set to a logic 1. the adc draws only 7a in sleep mode, provided that none of the digital inputs are switching. when convst returns low, the LTC2308 is released from the sleep mode and requires 200ms to wake up and charge the respective 2.2f and 10f bypass capacitors on the v ref and refcomp pins. board layout and bypassing to obtain the best performance, a printed circuit board with a solid ground plane is required. layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. care should be taken not to run any digital signal alongside an analog signal. all analog inputs should be shielded by gnd. v ref , refcomp and av dd should be bypassed to the ground plane as close to the pin as possible. maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the adc. these traces should be as wide as possible. see figure 7 for a suggested layout. applications information figure 7. suggested layout
LTC2308 17 2308f figure 8. LTC2308 timing with a long convst pulse applications information convst sck sdi 1 s/d o/s s1 s0 uni slp sdo msb hi-z lsb hi-z b1 b0 b3 b2 b5 b4 b7 b6 b9 b8 b11 b10 2308 f08 2345678910 t acq t conv 11 12 t wlconvst t cyc nap or sleep convst sdi 2308 f09 t acq t whconv t conv t cyc t hconvst s/d o/s s1 s0 uni slp sdo msb hi-z lsb hi-z b1 b0 b3 b2 b5 b4 b7 b6 b9 b8 b11 b10 sck 123456789101112 figure 9. LTC2308 timing with a short convst pulse
LTC2308 18 2308f figure 10. LTC2308 bipolar transfer characteristics (2s complement) input voltage (v) 0v output code (twos complement) C1 lsb 2308 f10 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 C 1lsb Cfs/2 fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv input voltage (v) output code 2308 f11 111...111 111...110 100...001 100...000 000...000 000...001 011...110 011...111 fs C 1lsb 0v unipolar zero fs = 4.096v 1lsb = fs/2 n 1lsb = 1mv figure 11. LTC2308 unipolar transfer characteristics (straight binary) applications information
LTC2308 19 2308f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?o be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 24 23 1 2 bottom view?xposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer
LTC2308 20 2308f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0807 ? printed in usa related parts typical application part number description comments ltc1417 14-bit, 400ksps serial adc 20mw, unipolar or bipolar, internal reference, ssop-16 package ltc1468/lt1469 single/dual 90mhz, 22v/s, 16-bit accurate op amps low input offset: 75v/125v ltc1609 16-bit, 200ksps serial adc 65mw, con? gurable bipolar and unipolar input ranges, 5v supply ltc1790 micropower low dropout reference 60a supple current, 10ppm/c, sot-23 package ltc1850/ltc1851 10-bit/12-bit, 8-channel, 1.25msps adc parallel output, programmable mux and sequencer, 5v supply ltc1852/ltc1853 10-bit/12-bit, 8-channel, 400ksps adc parallel output, programmable mux and sequencer, 3v or 5v supply ltc1860/ltc1861 12-bit, 1-/2-channel, 250ksps adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 3v, 12-bit, 1-/2-channel, 150ksps adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1863/ltc1867 12-/16-bit, 8-channel, 200ksps adc 6.5mw, unipolar or bipolar, internal reference, ssop-16 package ltc1863l/ltc1867l 3v, 12-/16-bit, 8-channel, 175ksps adc 2mw, unipolar or bipolar, internal reference, ssop-16 package ltc1864/ltc1865 16-bit, 1-/2-channel, 250ksps adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 3v, 16-bit, 1-/2-channel, 150ksps adc in msop 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com sdi sdo sck convst serial port analog input mux master clock convert enable refcomp 2308 ta02 internal 2.5v ref LTC2308 av dd dv dd ov dd gnd 0.1 m f 5v 12-bit 500ksps adc + C 0.1 m f 2.7v to 5v 2.2 m f 50 7 control logic (fpga, cpld, dsp , etc.) pre clr q q d v cc v cc convert enable nl17sz74 master clock nc7svu04p5x rf signal generator or other low-jitter source data transfer jitter 0.1 m f 0.1 m f 10 m f 10 m f 0.1 m f 10 m f v ref 1k 1k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? convst clock squaring/level shifting circuit allows testing with rf sine generator, convert re-timing flip-flop preserves low jitter clock timing

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